2.4 Real-Time Subsystem (RTSS)
The
The Cortex-M55 in the RTSS-HP can operate at up to 400 MHz core clock frequency. The single-cycle 256KB Instruction Tightly Coupled Memory (ITCM) and 1MB Data Tightly Coupled Memory (DTCM) enable a highly deterministic, high-performance execution environment capable of running tight control loops with minimal jitter. The RTSS-HP also has its own Ethos-U55 microNPU ML accelerator with capacity of 256 MACs. The faster clock frequency, larger TCM capacity, and increased number of MAC(s) in the RTSS-HP provide resources for implementation of advanced neural networks and faster, more accurate inference execution.
The implementation of the Cortex-M55 in the RTSS-HE is optimized for low current consumption while running at up to 160 MHz, and for extremely low leakage current while in STANDBY mode. This Cortex-M55 is equipped with 256KB ITCM and 256KB DTCM for fast single-cycle memory access (see Figure 2-5). The RTSS-HE resides in its own power domain and can operate standalone with minimum dependency on the other subsystems. Both the ITCM and DTCM contents can be optionally retained by a dedicated back-up power rail when the entire RTSS-HE power domain is powered off, enabling rapid wakeup. The RTSS-HE has a set of low power peripherals that can serve as a wakeup sources and that support ultra-low power application requirements. The Ethos-U55 microNPU includes 128 MACs and can be used for ML-based applications such as keyword spotting, simple image classification, anomaly detection, failure prediction, environmental sensing, and gesture recognition.
Figure 2-5 RTSS-HE Architecture